Top layers of metal for high performance IC&#39;s

ABSTRACT

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

[0001] This application is a continuation-in-part application of Ser.No. 09/216,791, filed on Dec. 21, 1998.

BACKGROUND OF THE INVENTION

[0002] (1). Field of the Invention

[0003] The invention relates to the manufacturing of high performanceIntegrated Circuit (IC's), and more specifically to methods of achievinghigh performance of the Integrated Circuits by reducing the parasiticcapacitance and resistance of interconnecting wiring on chip.

[0004] (2). Description of the Prior Art

[0005] When the geometric dimensions of the Integrated Circuits arescaled down, the cost per die is decreased while some aspects ofperformance are improved. The metal connections which connect theIntegrated Circuit to other circuit or system components become ofrelative more importance and have, with the further miniaturization ofthe IC, an increasingly negative impact on the circuit performance. Theparasitic capacitance and resistance of the metal interconnectionsincrease, which degrades the chip performance significantly. Of mostconcern in this respect is the voltage drop along the power and groundbuses and the RC delay of the critical signal paths. Attempts to reducethe resistance by using wider metal lines result in higher capacitanceof these wires.

[0006] To solve this problem, the approach has been taken to develop lowresistance metal (such as copper) for the wires while low dielectricmaterials are used in between signal lines.

[0007] Increased Input-Output (IO) combined with increased demands forhigh performance IC's has led to the development of Flip Chip Packages.Flip-chip technology fabricates bumps (typically Pb/Sn solders) on Alpads on chip and interconnect the bumps directly to the package media,which are usually ceramic or plastic based. The flip-chip is bonded facedown to the package medium through the shortest path. These technologiescan be applied not only to single-chip packaging, but also to higher orintegrated levels of packaging in which the packages are larger and tomore sophisticated substrates that accommodate several chips to formlarger functional units.

[0008] The flip-chip technique, using an area array, has the advantageof achieving the highest density of interconnection to the device and avery low inductance interconnection to the package. However,pre-testability, post-bonding visual inspection, and TCE (TemperatureCoefficient of Expansion) matching to avoid solder bump fatigue arestill challenges. In mounting several packages together, such as surfacemounting a ceramic package to a plastic board, the TCE mismatch cancause a large thermal stress on the solder-lead joints that can lead tojoint breakage caused by solder fatigue from temperature cyclingoperations.

[0009] U.S. Pat. No. 5,212,403 (Nakanishi) shows a method of formingwiring connections both inside and outside (in a wiring substrate overthe chip) for a logic circuit depending on the length of the wireconnections.

[0010] U.S. Pat. No. 5,501,006 (Gehman, Jr. et a].) shows a structurewith an insulating layer between the integrated circuit (IC) and thewiring substrate. A distribution lead connects the bonding pads of theIC to the bonding pads of the substrate.

[0011] U.S. Pat. No. 5,055,907 (Jacobs) discloses an extendedintegration semiconductor structure that allows manufacturers tointegrate circuitry beyond the chip boundaries by forming a thin filmmulti-layer wiring decal on the support substrate and over the chip.However, this reference differs from the invention.

[0012] U.S. Pat. No. 5,106,461 (Volfson et al.) teaches a multi layerinterconnect structure of alternating polyimide (dielectric) and metallayers over an IC in a TAB structure.

[0013] U.S. Pat. No. 5,635,767 (Wenzel et al.) teaches a method forreducing RC delay by a PBGA that separates multiple metal layers.

[0014] U.S. Pat. No. 5,686,764 (Fulcher) shows a flip chip substratethat reduces RC delay by separating the power and I/O traces.

SUMMARY OF THE INVENTION

[0015] It is the primary objective of the present invention is toimprove the performance of High Performance Integrated Circuits.

[0016] Another objective of the present invention is to reduce resistivevoltage drop of the power supply lines that connect the IC tosurrounding circuitry or circuit components.

[0017] Another objective of the present invention is to reduce the RCdelay constant of the signal paths of high performance IC's.

[0018] Yet another objective of the present invention is to facilitatethe application of IC's of reduced size and increased circuit density.

[0019] Yet another objective of the present invention is to furtherfacilitate and enhance the application of low resistor conductor metals.

[0020] Yet another objective of the present invention is to allow forincreased I/O pin count for the use of high performance IC's.

[0021] Yet another objective of the present invention is to simplifychip assembly by reducing the need for re-distribution of I/O chipconnections.

[0022] Yet another objective of the present invention is to facilitatethe connection of high-performance IC's to power buses.

[0023] Yet another objective of the present invention is to facilitatethe connection of high-performance IC's to clock distribution networks.

[0024] Yet another objective of the present invention is to reduce ICmanufacturing costs by allowing or facilitating the use of lessexpensive process equipment and by accommodating less strict applicationof clean room requirements, this as compared to sub-micron manufacturingrequirements.

[0025] Yet another objective of the present invention is to be a drivingforce and stimulus for future system-on-chip designs since the presentinvention allows ready and cost effective interconnection betweenfunctional circuits that are positioned at relatively large distancesfrom each other on the chip.

[0026] Yet another objective of the present design is to form the basisfor a computer based routing tool that automatically routesinterconnections that exceed a pre-determined length in accordance withthe type of interconnection that needs to be established.

[0027] The present invention adds one or more thick layers of dielectricand one or more layers of wide metal lines on top of the finished devicewafer. The thick layer of dielectric can, for example, be of polyimideor benzocyclobutene (BCB) with a thickness of over, for example, 3 um.The wide metal lines can, for instance, be of aluminum or electroplatedcopper. These layers of dielectric and metal lines can be used for powerbuses or power planes, clock distribution networks, critical signal,re-distribution of I/O pads for flip chip applications, and for longsignal paths.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028]FIG. 1 shows a cross section of the interconnection scheme of thepresent invention.

[0029]FIG. 2 shows a cross section of the present invention in a morecomplex circuit configuration.

[0030]FIG. 3a shows the top view of a combination power and X-signalplane using the present invention.

[0031]FIG. 3b shows the top view of a combination power and Y-signalplane using the present invention.

[0032]FIG. 4 shows the top view of solder bump arrangement using thepresent invention and is an expanded view of a portion of FIG. 5.

[0033]FIG. 5 shows the top view of an example of power/ground padscombined with signal pad using the present invention.

[0034]FIG. 6 shows a basic integrated circuit (IC) interconnect schemeof the invention.

[0035]FIG. 7 shows an extension of the basic IC interconnect scheme byadding power, ground and signal distribution capabilities.

[0036]FIG. 8 shows an approach of how to transition from sub-micronmetal to wide metal interconnects.

[0037]FIG. 9 shows detail regarding BGA device fan out using theinvention.

[0038]FIG. 10 shows detail regarding BGA device pad relocation using theinvention.

[0039]FIG. 11 shows detail regarding the usage of common power, groundand signal pads for BGA devices using the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0040] The present invention teaches an Integrated Circuit structurewhere key re-distribution and interconnection metal layers anddielectric layers are added over a conventional IC. Thesere-distribution and interconnection layers allow for wider buses andreduce conventional RC delay.

[0041] Referring now more specifically to FIG. 1, there is shown a crosssection of one implementation of the present invention. A siliconsubstrate 1 has transistors and other devices, typically formed of polysilicon, covered by a dielectric layer 2 deposited over the devices andthe substrate. Layer 3 indicates the totality of metal layers anddielectric layers that are typically created on top of the device layer2. Points of contact 6, such as bonding pads known in the semiconductorart, are in the top surface of layers 3 and are part of layer 3. Thesepoints of contact 6 are points within the IC arrangement that need to befurther connected to surrounding circuitry, that is to power lines or tosignal lines. A passivation layer 4, formed of for example siliconnitride, is deposited on top of layer 3, as is known in the art forprotecting underlying layers from moisture, contamination, etc.

[0042] The key steps of the invention begin with the deposition of athick layer 5 of polyimide is deposited. A pattern 7 is exposed andetched through the polyimide layer 5 and the passivation layer 4 wherethe pattern 7 is the same as the pattern of the contact points 6. Thisopens the contact points 6 up to the surface 8 of the polyimide layer 5.

[0043] Electrical contact with the contact points 6 can now beestablished by filling the openings 7 with a conductor. The tops 9 ofthis metal conductor can now be used for connection of the IC to itsenvironment, and for further integration into the surrounding electricalcircuitry. Pads 10, 11 and 12 are formed on top of the top 9 of themetal conductors 7; these pads can be of any design in width andthickness to accommodate specific circuit design requirements. A largersize pad can, for instance, be used as a flip chip pad. A somewhatsmaller in size pad can be used for power distribution or as a ground orsignal bus. The following connections can, for instance, be made to thepads shown in FIG. 1: pad 10 can serve as a flip chip pad, pad 11 canserve as a flip chip pad or can be connected to electrical power or toelectrical ground or to an electrical signal bus, pad 12 can also serveas a flip chip pad. There is no connection between the size of the padsshown in FIG. 1 and the suggested possible electrical connections forwhich this pad can be used. Pad size and the standard rules andrestrictions of electrical circuit design determine the electricalconnections to which a given pad lends itself.

[0044] The following comments relate to the size and the number of thecontact points 6, FIG. 1. Because these contact points 6 are located ontop of a thin dielectric (layer 3, FIG. 1) the pad size cannot be toolarge since a large pad size brings with it a large capacitance. Inaddition, a large pad size will interfere with the routing capability ofthat layer of metal. It is therefore preferred to keep the size of thepad 6 small. The size of pad 6 is however also directly related with theaspect ratio of via 7. An aspect ratio of about 5 is acceptable for theconsideration of via etching and via filling. Based on theseconsiderations, the size of the contact pad 6 can be in the order of 0.5um. to 3 um. the exact size being dependent on the thickness of layers 4and 5.

[0045] The present invention does not impose a limitation on the numberof contact pads that can be included in the design; this number isdependent on package design requirements. Layer 4 in FIG. 1 can be atypical IC passivation layer.

[0046] The most frequently used passivation layer in the present stateof the art is plasma enhanced CVD (PECVD) oxide and nitride. In creatinglayer 4, a layer of approximately 0.2 um. PECVD oxide is deposited firstfollowed by a layer of approximately 0.7 um. nitride. Passivation layer4 is very important because it protects the device wafer from moistureand foreign ion contamination. The positioning of this layer between thesub-micron process (of the integrated circuit) and the tens-micronprocess (of the interconnecting metalization structure) is of criticalimportance since it allows for a cheaper process that possibly has lessstringent clean room requirements for the process of creating theinterconnecting metalization structure.

[0047] Layer 5 is a thick polymer dielectric layer (for examplepolyimide) that have a thickness in excess of 2 um (after curing). Therange of polyimide thickness can vary from 2 um. to 30 um. dependent onelectrical design requirements.

[0048] For the deposition of layer 5 the Hitachi-Dupont polyimide HD2732 or 2734 can, for example, be used. The polyimide can be spin-oncoated and cured. After spin-on coating, the polyimide will be cured at400 degrees C. for 1 hour in a vacuum or nitrogen ambient. For thickerpolyimide, the polyimide film can be multiple coated and cured.

[0049] Another material that can be used to create layer 5 is thepolymer benzocyclobutene (BCB). This polymer is at this timecommercially produced by for instance Dow Chemical and has recentlygained acceptance to be used instead of typical polyimide application.

[0050] The dimensions of opening 7 have previously been discussed. Thedimension of the opening together with the dielectric thicknessdetermine the aspect ratio of the opening. The aspect ratio challengesthe via etch process and the metal filling capability. This leads to adiameter for opening 7 in the range of approximately 0.5 um. to 3.0 um.while the height for opening 7 can be in the range of approximately 3um. to 20 um. The aspect ratio of opening 7 is designed such thatfilling of the via with metal can be accomplished. The via can be filledwith CVD metal such as CVD tungsten or CVD copper, with electro-lessnickel, with a damascene metal filling process, with electroplatingcopper, etc.

[0051] It must be noted that the use of polyimide films as inter-leveldielectrics has been pursued as a technique for providing partialplanarization of a dielectric surface. Polyimides offer the followingcharacteristics for such applications:

[0052] they produce surfaces in which the step heights of underlyingfeatures are reduced, and step slopes are gentle and smooth.

[0053] they are available to fill small openings without producing thevoids that occur when low-temperature CVD oxide films are deposited.

[0054] the cured polyimide films can tolerate temperatures of up to 500degrees C. without degradation of their dielectric film characteristics.

[0055] polyimide films have dielectric breakdowns, which are onlyslightly lower than that of SiO₂.

[0056] the dielectric constant of polyimides is smaller than that ofsilicon nitride and of SiO₂.

[0057] the process used to deposit and pattern polyimide films isrelatively simple.

[0058] For all of the above characteristics, polyimides are used andrecommended within the scope of the present invention.

[0059]FIG. 2 shows how the present invention as indicated in FIG. 1 canbe further extended to include multiple layers of polyimide and, in sodoing, can be adapted to a larger variety of applications. The lowerlevel build up of this cross section is identical to the build up shownin FIG. 1 with a silicon wafer 1, the poly silicon layer 2, the metaland dielectric combined layer 3, the passivation layer 4, the polyimidelayer 5 and the pads 10 deposited on top of layer 5. The function of thestructure that has been described in FIG. 1 can be further extended bydepositing another layer of polyimide 14 on top of the previouslydeposited layer 5 and overlaying the pads 10. Selective etching andmetal deposition can further create contact points 12. These contactpoints 12 can be connected with pads 10 as shown by connector 13.Depositing pads 12 on top of layer 14 can thus further extend thisprocess. These pads 12 can be further customized to a particularapplication, the indicated extension of multiple layers of polyimidesgreatly enhances the flexibility and usefulness of the presentinvention. Additional alternating layers of polyimide and metal linesand/or power or ground planes may be added above layers 12 and 16, asneeded.

[0060]FIGS. 3a and 3 b show a top view of one possible use of thepresent invention. Interconnecting a number of pads 32 that have beencreated as described creates signal lines 30. Additional contact pointssuch as point 34 can allow signal lines to pass vertically betweenlayers. The various contact points can, for instance, be created withinthe surface of a power plane or ground plane 36. The layers within theinterconnecting metalization structure of the present invention cancontain signal interconnections in the X-direction, signalinterconnections in the Y-direction, signal interconnections between Xand or Y directions, interconnections to and/or within power and/orground buses. The present invention further teaches the interconnectionof signal lines, power and ground buses between the connected IC's andthe top of the metalization system of the present invention.

[0061]FIG. 3a shows signal lines formed in the X-direction, FIG. 3bshows signal lines formed in the Y-direction.

[0062]FIG. 4 presents yet another application of the present invention.Shown in FIG. 4 is an exploded view of a part of FIG. 5 that presents anarea array I/O distribution. FIG. 4 shows pads 41 (on which solder bumpscan be created) and an example of a layout of the redistribution of theperipheral pads 41′. The exploded view of FIG. 4 is taken along the line2-2′ shown in FIG. 5, the redistribution of the peripheral pads 41′ (seeFIG. 4) is, for clarity of overview, not shown in FIG. 5. The power orground connections can be made to any point that is required on thebottom device. Furthermore, the power and ground planes can be connectedto the power and ground planes of the package substrates. FIG. 4 showsan example of how to use the topmost metal layer to redistribute theperipheral pads 41′ to become area array pads 41. The solder bumps canthen be created on pads 41.

[0063]FIG. 5 shows the top surface of a plane that contains a designpattern of a combination of power or ground pads 52 and signal pads 54.FIG. 5 shows the pad openings in the top dielectric layer. It is to benoted that the ground/power pads 52 are heavier and larger in designrelative to the signal pads 54. The present invention ideally lendsitself to meeting these differences in design, as they are requiredwithin the art of chip and high performance circuit design. The numberof power or ground pads 52 shown in FIG. 5 can be reduced is there arepower and/or ground planes within the chip. From this it is clear thatthe package number of I/O's can be reduced within the scope of thepresent invention which leads to a reduction of the package cost byeliminating common signal/power/ground connections within the package.For instance, a 470 I/O count on a BGA chip can, within the scope of thepresent invention, be reduced to a 256 I/O count using the presentinvention. This results in considerable savings for the overall package.

[0064]FIG. 6 shows a basic design advantage of the invention. Thisadvantage allows for the sub-micron or fine-lines, that run in theimmediate vicinity of the metal layers 3 and the contact points 6, to beextended in an upward direction 20 through metal interconnect 7′, thisextension continues in the direction 22 in the horizontal plane of themetal interconnect 26 and comes back down in the downward direction 24through metal interconnect 7″. The functions and constructs of thepassivation layer 4 and the insulating layer 5 remain as previouslyhighlighted under FIG. 1. This basic design advantage of the inventionis to “elevate” or “fan-out” the fine-line interconnects and to removethese interconnects from the micro and sub-micro level to a metalinterconnect level that has considerably larger dimensions and istherefore with smaller resistance and capacitance and is easier and morecost effectively to manufacture. This aspect of the invention does notinclude any aspect of conducting line redistribution and therefore hasan inherent quality of simplicity. It therefore further adds to theimportance of the invention in that it makes micro and sub-micro wiringaccessible at a wide-metal level. The interconnections 7′ and 7″interconnect the fine-level metal by going up through the passivationand polymer or polyimide dielectric layers, transverses over a distanceon the wide-metal level and continues by descending from the wide-metallevel back down to the fine-metal level by again transversing downthrough the passivation and polymer or polyimide dielectric layers. Theextensions that are in this manner accomplished need not to be limitedto extending fine-metal interconnect points 6 of any particular type,such as signal or power or ground, with wide metal line 26. The laws ofphysics and electronics will impose limitations, if any, as to what typeof interconnect can by established in this manner where limiting factorswill be the conventional limiting factors of resistance, propagationdelay, RC constants and others. Where the invention is of importance isthat the invention provides much broader latitude in being able to applythese laws and, in so doing, provides a considerably extended scope ofthe application and use of Integrated Circuits and the adaptation ofthese circuits to a wide-metal environment.

[0065]FIG. 7 shows how the basic interconnect aspect of the inventioncan further be extended to now not only elevate the fine-metal to theplane of the wide-metal but to also add power, ground and signaldistribution interconnects of power, ground and signal planes at thewide-metal level. The wide-metal interconnect 26 of FIG. 6 is nowextended to further include an interconnection with the via 21. Intypical IC design, some pads may not be positioned in a location fromwhich easy fan-out can be accomplished to a location that is requiredfor the next step of circuit assembly. In those cases, the BGA substraterequires additional layers in the package construction in order toaccomplish the required fan-out. The invention teaches an approach thatmakes additional layers in the assembling of an IC feasible while notunduly increasing the cost of creating such a multi-layer interface.Ball formation 28 on the surface of interconnect 23 indicates how theinvention replaces part of the conventional BGA interconnect function,the solder bump provides for flip chip assembly. This interconnect 28now connects the BGA device with surrounding circuitry at the wide-metallevel as opposed to previous interconnects of the BGA device at thefine-metal level. The wide-metal interconnect of the BGA has obviousadvantages of cost of manufacturing and improved BGA device performance.By being able to readily extend the wide-metal dimensions it alsobecomes possible to interconnect power, ground and signal lines at awide-metal level thereby reducing the cost and complexity of performingthis function at the fine-metal level. The indication of 28 as a balldoes not imply that the invention is limited to solder bumps for makinginterconnects. The invention is equally applicable to wirebonding formaking circuit interconnects.

[0066]FIG. 8 further shows a cross section wherein the previous linearconstruction of the metal interconnection running through thepassivation layer and the insulation layer is now conical in form. Thesub-micron metal layer 60 is covered with a passivation layer 62, alayer 64 of polyimide or polymer is deposited over the passivation layer62. The wide metal level 66 is formed on the surface of layer 64. Thevia 70 is shown as having sloping sides, these sloping sides can beachieved by controlling the photolithography process that is used tocreated the via 70. The etching of the polyimide or polymer can forinstance be done under an angle of about 75 degrees with the followingcuring being done under an angle of 45 degrees. Also, a photosensitivepolyimide or polymer can be used, the cone shape of the via 70 can inthat case be achieved by variation of exposure combined with time ofexposure combined with angle of exposure. Where non-photosensitivepolymer or polyimide is used, a wet etch can be applied that has agradated faster and longer time etch as the top of the via 70 is beingapproached. The layer of wide-metal pad 68 is deposited on the surfaceof the polymer or polyimide layer 64, the wide-metal pad deposition 68mates with the top surface of the via 70 and is centered on top of thissurface.

[0067]FIGS. 9 through 11 show further detail to demonstrate the conceptsof BGA chip ball fan-out, pad relocation and the creation of commonground, power and signal pads.

[0068]FIG. 9 shows a cross section 100 of a BGA chip, five balls 101through 105 are also shown. By using the BGA substrate 106 and thewiring 107 within the substrate 106, it is clear that ball 101 can berepositioned to location 111, ball 102 to location 112, etc. for theremaining solder bumps 103 through 105. It is clear that the separationof contact points 111 through 115 is considerably larger than theseparation of the original solder bumps 101 through 105. The BGAsubstrate 106 is the subject of the invention, this substrate allows forspreading the distance between the contact points or balls of the BGAdevice to a considerable degree.

[0069]FIG. 10 shows the concept of pad relocation. BGA pad 120 can beany of the contact balls 101 through 105. By using the BGA substrate 130and the wiring 131 that is provided within the substrate, it is clearthat the BGA pads can be arranged in a different and arbitrary sequencethat is required for further circuit design or packaging. For instancecontact point 101, which is on the far left side of the BGA device 100,is re-routed to location 121 which is on the second far right of the BGAsubstrate 130. The re-arrangements of the other BGA solder bumps canreadily be learned from following the wiring 130 within the substrate131 and by tracing from solder bump to one of the contact points 122through 125 of the BGA substrate.

[0070]FIG. 11 shows the interconnecting of BGA device solder bumps intocommon power, ground or signal pads. The BGA chip 100 is again shownwith five solder bumps 101 through 105. The BGA substrate 130 contains awiring scheme that contains in this example three wiring units, one foreach for the power, ground and signal bumps of the BGA device. It isclear from FIG. 11 that wire arrangement 132 connects BGA device solderbumps 101, 103 and 105 to interconnect point 138 of the BGA substrate130. It can further be seen that BGA device solder bump 104 is connectedto interconnect point 140 of the BGA substrate by means of the wirearrangement 136, while BGA device solder bump 102 is connected tointerconnect point 142 of the BGA substrate by means of the wirearrangement 134. The number of pins required to interconnect the BGAdevice 100 is in this manner reduced from five to three. It is clearthat for more BGA device solder bumps, as is the case for an actual BGAdevice, the numeric effect of the indicated wiring arrangement isconsiderably more beneficial.

[0071] Some of the advantages of the present invention are:

[0072] 1) improved speed of the IC interconnections due to the use ofwider metal lines (which results in lower resistance) and thickerdielectrics between the interconnecting lines (which results in lowercapacitance and reduced RC delay). The improved speed of the ICinterconnections results in improved performance of High PerformanceIC's.

[0073] 2) an inexpensive manufacturing process since there is no needfor expensive equipment that is typically used in sub-micron ICfabrication; there is also no need for the extreme clean room facilitiesthat are typically required for sub-micron manufacturing.

[0074] 3) reduced packaging costs due to the elimination of the need forredundant I/O and multiple power and ground connection points that areneeded in a typical IC packaging.

[0075] 4) IC's of reduced size can be packaged and inter-connected withother circuit or system components without limiting the performance ofthe IC's.

[0076] 5) since dependence on ultra-fine wiring is reduced, the use oflow resistance conductor wires is facilitated.

[0077] 6) structures containing more complicated IC's can be createdbecause the invention allows for increased I/O pin count.

[0078] 7) more complicated IC's can be created without the need for asignificant increase in re-distribution of package I/O connections.

[0079] 8) power buses and clock distribution networks are easier tointegrate within the design of IC's.

[0080] 9) future system-on-chip designs will benefit from the presentinvention since it allows ready and cost effective interconnectionbetween functional circuits that are positioned at relatively largedistances from each other on the chip.

[0081] 10) form the basis for a computer based routing tool thatautomatically routes interconnections that exceed a predetermined lengthin accordance with the type of interconnection that needs to beestablished.

[0082] 11) provide a means to standardize BGA packaging.

[0083] 12) be applicable to both solder bumps and wirebonding for makingfurther circuit interconnects.

[0084] 13) provide a means for BGA device solder bump fan-out therebyfacilitating the packing and design of BGA devices.

[0085] 14) provide a means for BGA device pad relocation therebyproviding increased flexibility for the packing and design of BGAdevices.

[0086] 15) provide a means for common BGA device power, ground andsignal lines thereby reducing the number of pins required tointerconnect the BGA device with the surrounding circuits.

[0087] 16) provide a means for more relaxed design rules in designingcircuit vias by the application of sloped vias.

[0088] 17) provide the means for extending a fine-wire interconnectscheme to a wide-wire interconnect scheme without the need to apply apassivation layer over the surface of the fine-wire structure.

[0089] Although the preferred embodiment of the present invention hasbeen illustrated, and that form has been described in detail, it will bereadily understood by those skilled in the art that variousmodifications may be made therein without departing from the spirit ofthe invention or from the scope of the appended claims.

What is claimed is:
 1. A method for forming a top metalization system for high performance integrated circuits, comprising: forming an integrated circuit comprising a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting metalization structure connected to said devices and comprising a plurality of first metal lines in one or more layers; depositing a passivation layer over said interconnecting metalization structure; depositing an insulating, separating layer over said passivation layer that is substantially thicker than said passivation layer; forming openings through said insulating, separating layer and said passivation layer to expose upper metal portions of said overlaying interconnecting metalization structure; depositing metal contacts in said openings; and forming said top metalization system connected to said overlaying interconnecting metalization structure, wherein said top metalization system comprises a plurality of top metal lines, in one or more layers, each of said top metal lines having a width substantially greater than said first metal lines.
 2. The method of claim 1 wherein the top metalization system connects portions of said interconnecting metalization structure to other portions of said interconnecting metalization structure.
 3. The method of claim 1 wherein said top metalization system comprises signal lines that are substantially wider than lines in said interconnecting metalization structure.
 4. The method of claim 1 wherein said top metalization system comprises power planes having power buses that are substantially wider than lines in said interconnecting metalization structure.
 5. The method of claim 1 wherein said top metalization system comprises ground planes having ground buses that are substantially wider than lines in said interconnecting metalization structure.
 6. The method of claim 1 wherein said top metalization system comprises planes that contain both signal lines and power buses that are substantially wider than lines in said interconnecting metalization structure.
 7. The method of claim 1 wherein said top metalization system comprises planes that contain both signal lines and ground buses that are substantially wider than lines in said interconnecting metalization structure.
 8. The method of claim 1 wherein said top metalization system comprises planes that contain both power buses and ground buses that are substantially wider than lines in said interconnecting metalization structure.
 9. The method of claim 1 wherein said overlaying interconnecting metalization structure comprises electrical contact points.
 10. The method of claim 9 wherein the size of said contact points is within the range of approximately 0.3 um. to 5.0 um.
 11. The method of claim 1 wherein said passivation layer comprises Plasma Enhanced CVD (PECVD) oxide.
 12. The method of claim 1 wherein said passivation layer comprises Plasma Enhanced CVD (PECVD) nitride.
 13. The method of claim 1 wherein said passivation layer comprises a layer within the range of approximately 0.15 to 2.0 um of Plasma Enhanced CVD (PECVD) oxide over which a layer within the range of approximately 0.5 to 2.0 um PECVD nitride is deposited.
 14. The method of claim 1 wherein said insulating, separating layer is a polymer dielectric layer or any other appropriate insulating material.
 15. The method of claim 1 wherein said insulating, separating layer comprises polyimide.
 16. The method of claim 1 wherein said insulating, separating layer comprises the polymer benzocyclobutene (BCB).
 17. The method of claim 1 wherein said insulating, separating layer is of a thickness after curing within the range of approximately 1.0 to 30 um.
 18. The method of claim 1 wherein said insulating, separating layer is spin-on coated and cured.
 19. The method of claim 1 wherein said insulating, separating layer after said spin-on coating is cured at a temperature within the range of approximately 250 to 450 degrees C. for a time within the range of approximately 0.5 to 1.5 hours said curing to occur within a vacuum or nitrogen ambient.
 20. The method of claim 16 wherein said insulating, separating layer is subjected to multiple processing steps of spin on coating and curing.
 21. The method of claim 20 wherein said insulating, separating layer after each process step of said spin on coating is cured at a temperature within the range of approximately 250 to 450 degrees C. for a time within the range of approximately 0.5 to 1.5 hours said curing the occur within a vacuum or nitrogen ambient.
 22. The method of claim 1 wherein said openings have an aspect ratio within the range of approximately 1 to
 10. 23. The method of claim 1 wherein said metal contacts are selected from a group comprise sputtered aluminum, CVD tungsten, CVD copper, electroplated copper and electroless nickel.
 24. The method of claim 1 wherein said metal contacts comprise damascene metal filling.
 25. The method of claim 1 wherein said top metalization system comprises contact pads on the top metal layer whereby said contact pad can comprise any appropriate contact material, such as but not limited to tungsten, chromium, copper (electroplated or electroless), aluminum, polysilicon, or the like.
 26. The method of claim 1 wherein said top metal layer comprises contact pads, said contact pads comprising signal connection pads whereby said signal connection pads can comprise any appropriate contact material, such as but not limited to tungsten, chromium, copper (electroplated or electroless), aluminum, polysilicon, or the like.
 27. The method of claim 1 wherein said top metalization system contains contact pads on the top metal layer, said contact pads containing signal connection pads in addition to power and ground connection pads whereby said signal connection pads can comprise any appropriate contact material, such as but not limited to tungsten, chromium, copper (electroplated or electroless), aluminum, polysilicon, or the like.
 28. The method of claim 27 wherein said signal pads are mounted in the periphery of said top metalization system and said power and ground connection pads are mounted within the area enclosed by said signal pads whereby said power and ground connection pads and said signal pads can comprise any appropriate contact material, such as but not limited to tungsten, chromium, copper (electroplated or electroless), aluminum, polysilicon, or the like.
 29. A semiconductor device structure comprising: a semiconductor substrate comprising semiconductor devices; an interconnecting metalization structure connected to said devices; electrical contact points on an upper top surface of said interconnecting metalization structure and connected to said interconnecting metalization structure; a passivation layer deposited over said interconnecting metalization structure and over said electrical contact points; an insulating layer deposited over said passivation layer said insulating layer being substantially thicker than said passivation layer; openings through said insulating layer and through said passivation layer down to the upper surface of said electrical contact points; metal conductors within said openings; and an upper metalization structure connected to said metal conductors.
 30. The method of claim 29 wherein the upper metalization structure connects portions of said interconnecting metalization structure to other portions of said interconnecting metalization structure.
 31. The structure of claim 29 wherein said upper metalization structure further comprises: a plurality of insulating layers; a plurality of structures of metal interconnecting lines formed between said insulating layers; a plurality of contact pads in an upper layer of said metalization structure; and a plurality of filled openings connecting said contact pads with one or more of said structures of metal interconnecting lines further connecting said contact pads with said electrical contact points.
 32. The structure of claim 31 whereby said metal interconnecting lines are signal lines, and are substantially wider than lines in said interconnecting metalization structure.
 33. The structure of claim 31 wherein said metal interconnecting lines are power buses, and are substantially wider than lines in said interconnecting metalization structure.
 34. The structure of claim 31 wherein said metal interconnecting lines are ground buses, and are substantially wider than lines in said interconnecting metalization structure.
 35. The structure of claim 31 wherein said metal interconnecting lines are a combination of signal lines and power buses, and are substantially wider than lines in said interconnecting metalization structure.
 36. The structure of claim 31 wherein said metal interconnecting lines are a combination of power and ground buses, and are substantially wider than lines in said interconnecting metalization structure.
 37. The structure of claim 31 wherein said metal interconnecting lines are a combination of signal and ground buses, and are substantially wider than lines in said interconnecting metalization structure.
 38. The structure of claim 29 wherein the size of said contact points is within the range of approximately 0.3 um. to 5.0 um whereby further whereby said contact points can comprise any appropriate contact material, such as but not limited to tungsten, copper (electroplated or electroless), aluminum, polysilicon, or the like.
 39. The structure of claim 29 wherein said passivation layer comprises a layer within the range of approximately 0.15 to 2.0 um Plasma Enhanced CVD (PECVD) oxide over which a layer within the range of approximately 0.5 to 2.0 um PECVD nitride is deposited.
 40. The method of claim 29 wherein said insulating, separating layer is a polymer dielectric layer or any other appropriate insulating material.
 41. The method of claim 29 wherein said insulating, separating layer comprises polyimide.
 42. The method of claim 29 wherein said insulating, separating layer comprises the polymer benzocyclobutene (BCB).
 43. The structure of claim 29 wherein said insulating layer is of a thickness after curing within the range of approximately 1.0 to 30 um.
 44. The structure of claim 29 wherein said openings have an aspect ratio within the range of approximately 1 to
 10. 45. The method of claim 29 wherein said metal conductors within said openings through said insulating layer and through said passivation layer connecting said electrical contact pads of said top metalization structure with contact points of said interconnecting metalization structure are constructed and routed such that each said electrical contact point of said interconnecting metalization structure is connected directly and sequentially with one electrical contact point of said top metalization structure thereby creating a fan-out effect for said electrical contact point of said interconnecting metalization structure whereby the distance between said electrical contact points of said top metalization structure is larger than the distance between said electrical contact points of said interconnecting metalization structure by a measurable amount.
 46. The method of claim 29 wherein said the number of said electrical contact pads of said upper metalization structure can be larger than the number of said contact points of said interconnecting metalization structure by a considerable and measurable amount.
 47. The method of claim 29 wherein said metal conductors within said openings through said insulating layer and through said passivation layer connecting said electrical contact points of said top metalization structure with said contact points of said interconnecting metalization structure are constructed and routed such that each said electrical contact point of said interconnecting metalization structure is connected directly but not necessarily sequentially with one electrical contact point of said top metalization structure thereby creating a pad relocation effect for said electrical contact points of said interconnecting metalization structure whereby the distance between said electrical contact points of said top metalization structure is larger than the distance between said electrical contact point of said interconnecting metalization structure by a measurable amount whereby furthermore the sequence or adjacency of said electrical contact points of said interconnecting metalization structure is not necessarily the same as the sequence or adjacency between said electrical contact points of said top metalization structure.
 48. The method of claim 29 wherein said metal conductors within said openings through said insulating layer and through said passivation layer connecting said electrical contact points on a top surface of said top metalization structure with contact points of said interconnecting metalization structure are constructed and routed such that functionally identical electrical contact points of said interconnecting metalization structure are inter-connected and are connected with one electrical contact point or fewer electrical contact points of said top metalization structure thereby creating a reduction effect for said electrical contact points of said interconnecting metalization structure whereby the number of contact points for a particular electrical function within said electrical contact points of said top metalization structure is smaller than the number of said electrical contact points of said interconnecting metalization structure by a measurable amount whereby furthermore the sequence or adjacency of said electrical contact points of said interconnecting metalization structure is not necessarily the same as the sequence or adjacency between said electrical contact points of said top metalization structure.
 49. A method for forming a top metalization system for high performance integrated circuits, comprising: forming an integrated circuit comprising a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting metalization structure connected to said devices and comprising a plurality of first metal lines; depositing an insulating, separating layer over said semiconductor substrate; forming openings through said insulating, separating layer to expose upper metal portions of said interconnecting metalization structure; depositing metal contacts in said openings; and forming said top metalization system connected to said interconnecting metalization structure, wherein said top metalization system comprises a plurality of top metal lines, in one or more layers, having a width substantially greater than said first metal lines.
 50. The method of claim 49 wherein said top metalization system comprises signal lines that are substantially wider than lines in said overlaying interconnecting metalization structure.
 51. The method of claim 49 wherein said top metalization system comprises power buses that are substantially wider than lines in said interconnecting metalization structure.
 52. The method of claim 49 wherein said top metalization system comprises ground buses that are substantially wider than lines in said interconnecting metalization structure.
 53. The method of claim 49 wherein said top metalization system comprises planes that contain both signal lines and power buses that are substantially wider than lines in said interconnecting metalization structure.
 54. The method of claim 49 wherein said top metalization system comprises planes that contain both signal lines and ground buses that are substantially wider than lines in said overlaying interconnecting metalization structure.
 55. The method of claim 49 wherein said top metalization system comprises planes that contain both power buses and ground buses that are substantially wider than lines in said overlaying interconnecting metalization structure.
 56. The method of claim 49 wherein said overlaying interconnecting metalization structure comprises electrical contact points whereby said contact points can comprise any appropriate contact material, such as but not limited to tungsten, copper (electroplated or electroless), aluminum, polysilicon, or the like.
 57. The method of claim 56 wherein the size of said contact points is within the range of approximately 0.3 um. to 5.0 um.
 58. The method of claim 49 further comprising depositing a passivation layer over said interconnecting metalization structure.
 59. The method of claim 58 wherein said passivation layer comprises Plasma Enhanced CVD (PECVD) oxide.
 60. The method of claim 58 wherein said passivation layer comprises Plasma Enhanced CVD (PECVD) nitride.
 61. The method of claim 49 wherein said insulating, separating layer is a polymer dielectric layer or any other appropriate insulating material.
 62. The method of claim 49 wherein said insulating, separating layer is s elected from the group comprising polyimide and benzocyclobutene (BCB).
 63. A method for forming a top metalization system for high performance integrated circuits, comprising: forming an integrated circuit comprising a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting metalization structure connected to said devices and comprising a plurality of fine-wire metal lines; depositing a passivation layer over said interconnecting fine-wire metalization structure; depositing an insulating, separating layer over said passivation layer that is substantially thicker than said passivation layer; forming openings through said insulating, separating layer to expose upper metal portions of said overlaying interconnecting metalization structure; depositing metal contacts in said openings thereby raising a plurality of contact points in said overlaying interconnecting metalization structure to the top surface of said insulating, separating layer thereby creating elevated interconnecting metalization contact points; forming said top metalization system connected to said overlaying interconnecting metalization structure, wherein said top metalization system comprises a plurality of top wide-metal lines, in one or more layers, having a width substantially greater than said fine-wire metal lines, wherein said top metalization system directly interconnects said elevated interconnecting metalization contact points thereby functionally extending or connecting said fine-wire metal interconnects with said wide-wire metal interconnects thereby furthermore establishing electrical interconnects between multiple points within said fine-wire interconnects.
 64. The method of claim 63 wherein said top metalization system comprises signal lines that are substantially wider than lines in said interconnecting metalization structure.
 65. The method of claim 63 wherein said top metalization system comprises power planes that are substantially wider than lines in said interconnecting metalization structure.
 66. The method of claim 63 wherein said top metalization system comprises ground planes that are substantially wider than lines in said interconnecting metalization structure.
 67. The method of claim 63 wherein said passivation layer comprises Plasma Enhanced CVD (PECVD) oxide.
 68. The method of claim 63 wherein said passivation layer comprises Plasma Enhanced CVD (PECVD) nitride.
 69. The method of claim 63 wherein said insulating, separating layer is a polymer dielectric layer or any other appropriate insulating material.
 70. The method of claim 63 wherein said insulating, separating layer comprises polyimide.
 71. The method of claim 63 wherein said insulating, separating layer comprises the polymer benzocyclobutene (BCB).
 72. The method of claim 63 wherein said insulating, separating layer is of a thickness after curing within the range of approximately 1.0 to 30 um.
 73. The method of claim 63 wherein said insulating, separating layer is spin-on coated and cured.
 74. The method of claim 63 wherein said openings have an aspect ratio within the range of approximately 1 to
 10. 75. The method of claim 63 wherein said metal contacts is selected from the group comprising sputtered aluminum, CVD tungsten, CVD copper, electroplated copper, electroless nickel and damascene metal filling.
 76. The method of claim 63 wherein said openings through said insulating, separating layer have sloped sides and wherein each of said openings is wider at its top.
 77. The method of claim 63 thereby furthermore functionally and physically extending said top metalization system connected to said overlaying interconnecting metalization structure, wherein said top metalization system comprises a plurality of ground planes, in one or more layers, wherein furthermore said overlaying interconnecting metalization structure directly interconnects a multiplicity of ground wires said ground wires to be connected with fine-wire ground wires thereby functionally extending or connecting said fine-wire ground wire metal interconnects with said wide-wire metal ground wire interconnects contained within said top metalization system thereby extending the fine-wire ground wires as contained within the overlaying interconnecting metalization structure with said top metalization system.
 78. The method of claim 63 thereby furthermore functionally and physically extending said top metalization system connected to said overlaying interconnecting metalization structure, wherein said top metalization system comprises a plurality of signal planes, in one or more layers, wherein furthermore said overlaying interconnecting metalization structure directly interconnects a multiplicity of signal wires said signal wires to be connected with fine-wire signal wires thereby functionally extending or connecting said fine-wire signal wire metal interconnects with said wide-wire metal signal wire interconnects contained within said top metalization system thereby extending the fine-wire signal wires as contained within the overlaying interconnecting metalization structure with said top metalization system.
 79. The method of claim 63 thereby furthermore functionally and physically extending said top metalization system connected to said overlaying interconnecting metalization structure, wherein said top metalization system comprises a plurality of power planes, in one or more layers, wherein furthermore said overlaying interconnecting metalization structure directly interconnects a multiplicity of power wires said power wires to be connected with fine-wire power wires thereby functionally extending or connecting said fine-wire power wire metal interconnects with said wide-wire metal power wire interconnects contained within said top metalization system thereby extending the fine-wire power wires as contained within the overlaying interconnecting metalization structure with said top metalization system. 